Bolt, Beranek and Newman (BBN)
Bolt, Beranek and Newman (BBN)
Status
Active and now a divison of
GTE Internetworking.
Overview of Organisation
BBN was founded in 1948 as an
acoustic consultancy company and has since diversified into computing
and communications. Amongst other things BBN were involved in
producing the ARPAnet communications system. BBN's first parallel
processing platform was the Pluribus, a multi-bus machine using a
number of interconnected Lockheed SUE minicomputers, which was
designed as a node for ARPAnet. In 1978, BBN was commissioned by
DARPA to produce a new parallel computer system, with special emphasis
on the communications switching technology upon which the machine
would be based. This switch became known as the butterfly because its
wiring topology is similar in structure to the FFT butterfly layout.
The butterfly still forms the basis for BBN computers.
The original butterfly machine was redesigned to be aimed at the
time-critical systems market and as such was redesignated the TC2000
(TC standing for Time Critical). At the same time, some upgrades to
the original machine were made and this became known as the GP1000,
(GP standing for General Purpose).
Platforms Documented
Contact Address
Bolt, Beranek and Newman Advanced Computers Inc.
10 Fawcett Street
Cambridge MA 02138, USA.
Tel (617) 873 6000
Fax (617) 873 3315
BBN Inc.
Heriot-Watt Research Park
Riccarton
Edinburgh EH14 4AP
Scotland
031-449-5488
Company's homepage.
See Also
BBN have a
commercial server entry in the
Global Network Navigator
and also support a server for
BBN
Systems and Technologies DIS Dept .
.
BBN Butterfly
Overview of Platform
The Butterfly was commissioned
specifically by DARPA to investigate the switching technology upon
which the machine would be based.
This machine was upgraded to the Butterfly-Plus, which was later
redesignated as the GP1000.
Parallel Butterfly Network Architecture.
Compute Hardware
Motorola 68000-series microprocessors.
Interconnect / Communications System
Butterfly switch consisting of a set of 4 by 4 crossbar switch
modules. This is inferior (but cheaper) than a full crossbar, and
gives better performance for a practical number of processors than
would a bus based communications system.
Memory System
500kBytes of memory per processor.
Benchmarks / Compute and data transfer performance
N/A
Operating System Software and Environment
N/A
Networkability/ I/O System / Integrability / Reliability /
Scalability
The Butterfly was configured as a compute engine
with a front-end host machine on which user code was developed.
Notable Applications / Customers / Market Sectors
Between
30 and 40 systems were sold, mostly to universities, interested in the
machine's novel architecture.
Overall Comments
The butterfly switch is undoubtedly the most noteworthy feature of this machine.
BBN GP1000
Overview of Platform
The Butterfly
evolved into the Butterfly-plus, which no longer had a fron-end host
and provided its own operating system - namely the MACH UNIX developed
by Carnegie Mellon University
The Butterfly was also redesignated as the general purpose GP1000.
The Butterfly GP1000 is a tightly coupled, shared memory
multiprocessor housing up to 256 processor boards, each with an
MC68020 microprocessor and an IEEE-complying MC68882 floating-point
coprocessor. Every processor board includes 4 Mbytes of globally
shared memory. Any processor can access any memory location through
the Butterfly switch, a fast, modular, multi-stage interconnect.
Processors also have direct access to their own 4 Mbyte share of the
global memory pool. Providing true parallel access to memory, the
Butterfly performs up to 256 simultaneous reads or writes and
automatically resolves contention for memory.
Other architectural features include:
Multiple instruction, multiple data (MIMD) architecture.
Up to 600 mips of processing power in 2.5 mip increments.
All processors have access to as much as 1024 Mbytes
(one Gbyte) of main memory.
Memory bandwidth up to 1024 Mbytes/sec (one Gbyte/sec).
Memory access time is typically less than 1 microsecond,
(4 microseconds worst case --- without contention. )
Distributed I/O system supports RS-232, RS-449, Ethernet, Multibus,
and VME bus.
Field expandable in single processor increments.
Compute Hardware
Motorola 68020 series microprocessors.
Interconnect / Communications System
Butterfly switch
consisting of a set of 4 by 4 crossbar switch modules. This is
inferior (but cheaper) than a full crossbar, and gives better
performance for a practical number of processors than would a bus
based communications system.
Memory System
4Mbytes of memory per node.
Benchmarks / Compute and data transfer performance
N/A
Operating System Software and Environment
MACH Unix
developed by Carnegie Mellon University was used on the GP1000.
Software includes: Mach 1000, the GP1000 operating system, is based on
Berkeley 4.3bsd UNIX, with extensions for parallel processing. The
GP1000 supports C, Fortran 77, Common Lisp, and Scheme (a Lisp
dialect). Ada is being developed. All languages are extended naturally
to support parallel structures. A rich, graphically-oriented debugging
environment is provided.
Networkability/ I/O System / Integrability / Reliability /
Scalability
No front end host was used on the GP1000, the
operating system was implemented directly on node processors.
The GP1000 is a standalone system supporting a full range of
peripherals including 500 Mbyte and 850 Mbyte disk drives; 1/4"
cartridge and 1/2" reel-to-reel tape drives; a flexible terminal
control system; and an Ethernet interface.
Notable Applications / Customers / Market Sectors
Approximately 60 GP1000's are believed to have been sold, some 75% to
universities.
Overall Comments
This machine seems to have been succesful
in attracting sales, albeit to universities and other organisations
interested in experimenting with the architecture rather than as a
standard compute engine.
BBN TC2000
Overview of Platform
The TC2000 was introduced in July 1989
and by 1991 was the only BBN machine being actively marketed.
The TC2000 is a shared memory, medium grained, MIMD computer on whose
individual processors the user runs different tasks. The machine may
be partitioned into autonomous clusters, to allow multiple
applications to be run concurrently. Cluster allocation and
management is dynamic so extra processors from the pool can be
allocated to especially intensive jobs.
The multiprocessing architecture of the BBN TC2000 allows
field-expansion from eight to 504 processors, with corresponding
increases in memory, memory-access bandwidth, and I/O capabilities.
TC2000 system supports two operating systems concurrently. At the
same time as some processors are running the pSOS+m real-time
executive for time-critical applications, others can be using the
nX operating system (based on UNIX 4.3 BSD) for either
analysis or time-shared program development.
A major feature unique to the TC2000 system is its software-
controlled clustering capability. Processors can be assigned to
groups or clusters, which are then designated for either nX or
pSOS+m operation. Different sections of an application can be run
concurrently on each one. In addition, data can be shared within
and between clusters, so a TC2000 system can integrate various
segments of a complex application traditionally dispersed among a
number of loosely-coupled computers. Processor allocation is
dynamic, meaning that resources can be reallocated during an
actual run.
To reduce the time and cost of applications development, the
TC2000 system includes the only graphical development tools
specifically designed for a multiprocessor environment. Based on
the X Window System standard, the Xtra (X Tools for
Runtime Analysis) environment makes it easier for programmers to
handle the complexities inherent in multiprocessor programming.
Included within the Xtra environment is the TotalView source-
level, multi-processing debugger and the Gist graphics-
oriented performance analyzer. Optimized Ada, Fortran-77 and C
compilers are also available for the TC2000 system.
Compute Hardware
Motorola 88000-series RISC chips. A node
is made up ofan 81000 processor with three 88200 cache/memory
management chips and the Butterfly switch interface.
Interconnect / Communications System
Butterfly switch
consisting of a set of 8 by 8 crossbar switch modules. This is
inferior (but cheaper) than a full crossbar, and gives better
performance for a practical number of processors than would a bus
based communications system. A two stage 8 by 8 crossbar allows a
maximum of 64 nodes in the machine, but by using a 3 stage switch this
can be increased to 512 nodes.
Memory System
Each node has either 4 or 16MBytes of memory,
and the three 88200 chips all have 16kBytes of four-way associative
cache memory.
Benchmarks / Compute and data transfer performance
The peak
I/O rate for a 64 node machine is determined by that of the VME
interfaces and is quoted as 320MBytes per second.
MAXIMUM SYSTEM PERFORMANCE (504 processors)
Integer 9,576 Dhrystone MIPS
Whetstone 6,552 Whetstones
Floating Point 10,080 MFLOPS
Memory 16,096 MBytes
I/O Bandwidth 2,560 MBytes/sec
Operating System Software and Environment
Message routing
through the butterfly switch is based on a network packet routing
system. The operating systems provided are based either on UNIX or on
a proprietary system designed for real time applications.
Performance monitoring and debugging facilities toolsets are also
provided.
Disk access is through a SCSI system connected to the VME bus on each
node.
Sustainable rates of 7MFLOPS per node have been reported independently
of BBN.
Networkability/ I/O System / Integrability / Reliability /
Scalability
Each TC2000 has at least one VME interface to
support attached graphics devices and disks, and up to 5 VME
interfaces can be used on one switch module, thus increasing the
available bandwidth which is important for time critical applications.
Notable Applications / Customers / Market Sectors
The real
time or time-critical applications market is what the TC2000 was
targetted at. At least 12 systems are known to have been sold.
Overall Comments
This machine embodies some interesting
ideas in switch networking but it is difficult to see how the
butterfly switch can be scaled to very large sizes in a cost effective
manner.
hawick@npac.syr.edu
saleh@npac.syr.edu