Bull

Status

The company is no longer marketing supercomputers. In March 1998, the company signed an agreement with NEC to market the

SX supercomputers throughout France.

Overview of Organisation

The Isis supercalculateur was designed after an extensive survey of French computational scientists to ascertain their principal requirements for a supercomputer. Although constructed and marketed by the Bull company, it can be thought of as a French national project.

Platforms Documented

ISIS

Contact Address

Bull DRTG
Rue Jean Jaures
78340 Les Clayes-sous-Bois
France

Company's homepage.

ISIS

Overview of Platform

Pipelined vector processor with multiple processing elements RISC architecture.

Compute Hardware

Central processing unit consisting of four independent scalar elements connected to one vector unit. Each scalar processor has its own units for floating-point and integer operations, 256 general registers with three simultaneous accesses and a cache of 256 instructions to handle branch conditions. The cycle time for these scalar units is 15 nsec, and they are rated at 33 mips. The scalar unit can initiate (or spawn off) tasks to the vector unit.

There are 8 to 32 elementary processors, which can function simultaneously, in the vector unit. Elements of a vector are normally (and automatically) assigned across the processors in a wraparound (or folded) fashion. Each processor can do a floating-point or integer operation every 30 nsec and has 256 registers to store scalars or vectors. Logic is in 100K gate arrays, with 2,500 gates on chip. Delay time is 350 picoseconds. Each vector processor has a peak performance of 33 Mflops.

Interconnect / Communications System

Memory System

Main memory of 8 Mwords (64-bit words), arranged in 16 interleaved banks with a throughput rate of 266 Mwords/sec. Memory is in static MOS with a 35 nsec cycle time. There is hardware indirect addressing.

The secondary memory has up to 64 Mwords (64-bit words) with a possible extension to 256 Mwords. Its speed is the same as the main memory but with a latency time four times as great. It is accessed in blocks and used as an I/O cache. Secondary memory is in dynamic MOS with a 120 nsec cycle time.

Benchmarks / Compute and data transfer performance

Operating System Software and Environment

The following software was available: Bull's own version of UNIX. Batch oriented, Math library under development. BLAS, IMSL, and NAG are available.

Languages: Fortran 8x, Assembler. Pacific Sierra VAST-2 was available.

Networkability/ I/O System / Integrability / Reliability / Scalability

The machine could be configured with:

The I/O controller is built around an SPS7 machine and manages
the 4 Gbytes of fast-memory disks. Its peak speed is 100 Mbytes/sec.
The I/O controller communicates with the outside world through a
hyperchannel.

The Isis is connected to its front-end machine through the hyperchannel.

Notable Applications / Customers / Market Sectors

Principal applications covered by the survey included finite-element techniques, finite-difference methods, spectral methods, and Monte Carlo calculations.

Overall Comments

hawick@npac.syr.edu

saleh@npac.syr.edu