Control Data Corporation

Control Data Corporation

Status

Active but no longer in the computer hardware business.

Overview of Organization

Platforms Documented

Contact Address 

Control Data Systems, Inc. 
4201 Lexington Avenue North 
Arden Hills, MN 55126-6198
Company's homepage.

See Also

CDC CYBER 180 990E/995E

Overview of Platform

Vector Architecture.

Compute Hardware

Each processor has a 16 nsec clock, a 32 Kbyte data cache, and an instruction cache of 64 instruction words (equivalent to a maximum of 256 instructions). There are no vector registers. There are segmented functional units for addition/subtraction, multiplication, scalar multiplication, division (4 units), shift, integer addition/subtraction, compare, Boolean, increment, and character handling. There is shortstopping (that is, effectively chaining) but no scalar/vector overlap.

Interconnect / Communications System

Memory System

The memory size is from 16 to 256 Mbytes in 32 banks of 256 Kbit static MOS. There are four ports to memory, 2 for the CPUs and 2 for I/O. The bank busy time is 96 nsec. The virtual address space is 8.8 trillion words/user.

Each system has from 8 to 256 MWords (64-bit words) of MOS semiconductor shared memory using 256K DRAMS. Memory sizes ares 8, 16, 32, 64, 128, or 256 million words. There is a 1 MWord fast communication buffer for interprocessor communication and synchronization. The system has virtual memory addressing using a 48-bit address. SECDEC is on each 32-bit half word. The maximum transfer rate is 1 word per clock cycle between each CPU and shared memory.

Benchmarks / Compute and data transfer performance

The peak performance of the 992 is 125 Mflops.

Operating System Software and Environment

Software: ETA System V: EOS: Utilities included: Interactive symbolic debugger; Symbolic postmortem dump Performance analyzer; Source and object code maintenance.

Many matrix algebra routines are available, including the BLAS in the LIB99 vectorized subroutine library. Also, an object code utility called Afterburner is available that provides user-selected in-lining of system and user subroutines for reduction of call/return overhead.

The operating system is NOS/VE and languages supported include Fortran, Cobol, Lisp, Prolog, Pascal, C, Cybil, Basic, and APL. There is a hot spot analyzer available for Fortran codes. The Fortran compiler allows many extensions including some anticipated 8x constructs and generates vector code automatically. Compiler directives are also available.

Networkability/ I/O System / Integrability / Reliability / Scalability:

It is possible to do a field upgrade from the one-processor 992-31 to the two-processor 992-32. Up to 18 440 Mbit/sec I/O units are available for accessing disks, tapes, other mainframes, and networks. There is a dual-ported interface to 1.2 Gbytes (formatted) capacity disks with a data transfer rate of 12 Mbytes per second, an average seek time of 16 milliseconds, and an average latency of 8.3 milliseconds. Each IOU can support up to 16 such drives. Each IOU also can interface to as many as 20 1.1 Gbyte capacity, 3 Mbytes per second SMD disks. There are connections to 10 Mbit/sec Ethernet using TCP/IP, CDC's 50 Mbit/sec. Loosely Coupled network (LCN) using RHF and a 50 Mbit/sec hyperchannel using TCP/IP. The series can have a variety of front-ends including CDC, IBM, and DEC. It can also operate stand-alone, with access from terminals and workstations via Ethernet.

Notable Applications / Customers / Market Sectors

N/A

Overall Comments

CYBER 205

Overview of Platform

Vector Architecture.

Compute Hardware

Architecture: ECL/LSI logic (168 gates/chip) Sequential and parallel processing on single bits, 8-bit bytes and 32- or 64-bit floating-point operands 20-nsec cycle time Scalar Unit Segmented functional units 64-word instruction stack 256 word high-speed register file Vector Unit 1, 2, or 4 segmented vector pipelines memory-to-memory data streaming maximum vector length of 65,536 words gather/scatter instructions up to 800 million 32-bit floating-point operations/second

Interconnect / Communications System

Memory System 

 Memory
  MOS semiconductor memory
  Memory size:  1, 2, 4, 8 or 16 million 64-bit words
  Virtual memory accessing mechanism with multiple, concurrently
 usable page sizes
  SECDED on each 32-bit half word
  48-bit address (address space of 4 trillion words per user)
  80 nsec memory bank cycle time
  Memory bandwidth:  25.6 or 51.2 Gigabits/second

Benchmarks / Compute and data transfer performance 

Performance:
 Linked triad performance on long vectors approaches asymptotic
  speed of machine.
 Performance can be severely degraded at short vector lengths
  (that is, the typical $n _ {1/2}$ is around 100), and if
  vector is not held contiguously.  For this reason most
  tuned software employs long, contiguously held vectors.

Operating System Software and Environment 

Software:
 Virtual operating system
 Batch and interactive access
 FORTRAN compiler
  ANSI 77 with vector extensions
  32-bit half-precision data type
  Special calls to machine instructions
  Automatic vectorization
  Scalar optimization utilizing large register file

 Utilities
  Interactive symbolic debugger
  Source code maintenance
  Object code maintenance

Networkability/ I/O System / Integrability / Reliability / Scalability 

 I/O
  Eight I/O ports, 32-bits in width, expandable to 16
  200 Mbits/second for each port
  Maximum I/O port bandwidth of 3200 Mbits/sec

 Miscellaneous
  Cooling:  freon
  Dimensions:  floor area (four pipe model) 23 ft x 19 ft
   footprint (with I/O system) 105 sq ft

Notable Applications / Customers / Market Sectors

N/A

Overall Comments

N/A

CYBERPLUS

Overview of Platform

Ring Bus Architecture This is a multiple parallel processor system. It grew from the Flexible Processor Project and the subsequent Advanced Flexible Processor Project (AFP), used in military applications since 1976. The machine is based on ring technology with an 800 Mbits/second transfer rate, with a read and a write possible between processors at this sustained rate. There are two CYBERPLUS processor modes: 16-bit integer and 32- and 64-bit floating point. The integer processor has 15 independent functional units capable of 8-, 16- an 32-bit working; each processor has a 20-nsec cycle time. The floating-point processor is an extension of the integer one through the addition of three floating-point functional units capable of 32- and 64-bit precision, with rated maximum performance of 65 Mflops (103 in 32-bit mode).

Compute Hardware

Each processor contains 2048 Kbytes of memory which can be expanded to 4096 Kbytes. A crossbar architecture allows the output of one functional unit to go to any or all other functional units in one machine cycle and permits all functional units to fire every cycle. The independent functional units are as follows: 


 - 1 program unit
 - 9 I/O units including 4 read/write 16-bit memory units
 - 2 read/write 64-bit memory units, 2 ring port I/O units,
 - 5 integer/Boolean units (2 add/subtract, 1 multiply, and
     2 shift Boolean)
Floating point: 1 add/subtract, 1 multiply, 1 divide/square root connected by an additional crossbar. Floating-point units can run simultaneously with fixed-point ones.

Each instruction can initiate multiple functional units.

Up to 16 rings can be connected to a CYBER 800 computer (each connected through a channel ring port) with up to 16 CYBERPLUS processors per ring. Within this ring all processors can operate autonomously and may execute each clock cycle. Processor Memory Interface allows direct reading and writing of the memory of any processor by another processor on the ring every machine cycle. Central Memory Interface (CMI) for transfer of data to host. The central memory ring is 64 bits wide with an 80 nsec cycle time, and this provides a direct transfer of 64 bits between the CYBER and a CYBERPLUS processor. Data transfers are controlled by the system ring and will be direct memory-to-memory transfers with the HPM memory on the CYBERPLUS processors. Two rings connect the processors: the system ring and the application ring. The ring packet has 13 bits of control information and 16 bits of data. A function code in the ring packet can determine whether access to other memories (one or several) is direct or indirect, the latter requiring the acceptance by the target processor. 

There are three distinct memory systems:

  1. 4K 16-bit data memory: 4 independent bipolar data
    memories with a one-cycle read/write.
  2. 256K 64-bit high-performance data memory: 4 banks with
    4-cycle memory access, expandable to 512K 64-bit words
    with 8 banks.
  3. Program Instruction Memory with 4096 200-bit words. Each
    machine cycle, the instruction memory fetches and
    initiates the execution of one or all of the parallel
    functional units. When the floating-point option is in
    use, the size of these memory words increases to 240 bits.
    The program instruction memory is expandable to 16K words.

The host CDC 170 Series 800 (under NOS 2) loads code into the processors, transmits data from host to processors, and starts and stops processor's task. Software includes a cross assembler (MICA), a CYBERPLUS instructor load simulator (ECHOS), and an ANSI 77 Fortran cross-compiler.

64-bit floating point is 14 decimal accurate with a range of 10^-293 to 10^+322. 32-bit is 7 decimal accurate with range $10 ^ {-39}$ to $10 ^ {+37}$.

Interconnect / Communications System

n/a

Memory System

n/a

Benchmarks / Compute and data transfer performance

Claimed performance of 64 CYBERPLUS systems linked to a single Control Data 170 Series 800 is 16 billion calculations per second on signal data applications. Change detection algorithm for image processing is about 100 times faster than on a CDC 7600.

Operating System Software and Environment

Announced formally on October 4, 1983; floating-point hardware and software delivered in first quarter 1985. Fortran compiler available for research activities fourth quarter 1984 and released April 1985.

Networkability/ I/O System / Integrability / Reliability / Scalability

n/a

Notable Applications / Customers / Market Sectors

n/a

Overall Comments

n/a

hawick@npac.syr.edu
saleh@npac.syr.edu