Devices resulting from evolutionary progression of complementary metal oxide semiconductor (CMOS) technology are most likely to be used in PetaFLOPS systems. CMOS dominates current device technology, and enjoys very high levels of continuous world-wide investment. It is pervasive with an infrastructure in place to support every aspect of research, development, design, and application. Also, the technology is sufficiently well understood that future device capabilities can be predicted with only modest risk. Asserting the merits of CMOS, however, is not a recommendation to ignore other device approaches. Research and development over the next two decades will result in new high-performance device technologies which may be well suited for PetaFLOPS computing systems. Proposed alternative approaches will be measured against the CMOS option, and they must show significant advantages over CMOS to be given serious consideration.
The working group explored expectations for deep submicrometer feature size CMOS devices and identified the 0.05 micrometer technology generation as capable of supporting PetaFLOPS machines in about the 2015 time frame. Also, it is possible that PetaFLOPS machines can be built earlier using larger feature size technology-if circuit design and architectural schemes provide added performance. Using the 0.05 micrometer technology as a reference point, the viability of the physical, electrical, and thermal aspects of a PetaFLOPS machine were considered.
The potential for using future CMOS technology to build PetaFLOPS machines was examined in four phases. First, the characteristics of existing and emerging processor devices were reviewed. Second, the scope of existing technology predictions was evaluated. Third, focused scaling and engineering judgment device predictions were developed. Finally, the utility of the predicted device technology for PetaFLOPS machines was examined.