Superconducting device technology offers the prospect of clock speeds one to two orders-of-magnitude faster than competing semiconductor devices and, perhaps more importantly, with power consumption requirements one to two orders-of-magnitude lower. These combined features are both critical to the viability of PetaFLOPS computing and place superconducting components among the key contending technologies considered by the Device Technology Working Group. Detracting from the opportunities afforded by superconductivity are the requirements for maintaining and interfacing a supercooled environment (currently 4 Kelvins) and minimal ongoing U.S. industrial R&Dinvestment in this area. The lack of funding is, as usual, a function of market forces. There is no strong market niche in which superconductive computing devices are essential, although some exotic sensors do operate in this regime. Thus, superconductivity is an example of a potentially important enabling technology for PetaFLOPS computing that currently does not benefit a strong market-driven support base.
Experimental sub-systems employing superconducting technology have demonstrated
feasibility of implementing the primary constituents for high-performance
computing. Logic, memory, and interconnect devices have been fabricated and
exhibit superior performance characteristics compared to their semiconductor
counterparts. Logic devices have been implemented using
lithography permitting VLSI level chips to be implemented although at
an order-of-magnitude lower density than state-of-the-art semiconductor
devices. Gate delays are at a few picoseconds permitting a
multi-GigaHertz supercomputer processor to be built today. Power
dissipation per gate, even at these very high switching rates is on the
order of microwatts. RAM chips with 4K bits have been demonstrated with
access times of 0.5 nanoseconds. At present,
RAM chips are under
development, with access times of 0.1 to 0.2 nanoseconds likely in the
near future. Superconducting metalization makes ideal transmission lines
with extremely low cross-coupling resulting in very low dispersion and
loss. Interchip interconnections for Multi-Chip Modules (MCM) have been
designed to support throughputs at between 1 and 10 GHz rates.
Many of these advances have been achieved in Japan where a prototype
supercomputer processor implemented using superconducting technology is
being developed by ETL.
One challenge to the effective use of systems incorporating this technology is its interface to ambient temperature external environments. Here, the use of free-space optical interconnects may prove most appropriate providing high data rate paths with no corresponding thermal transport medium. A second problem is the relatively low density of superconducting memory compared to that being realized through semiconductors. Purely superconductive memory is not expected to significantly exceed 64K bits although some indications are that this might be pushed to the megabit per chip level. This is sufficient for registers, buffers, and caches to be used within a superconducting supercomputer. But a higher density memory technology such as semiconductor must provide main memory for any such system.
Leveraging existing techniques and advancing fabrication methods for superconducting devices should enable the development of a 50 GigaFLOPS superconducting processor within the next five years. Such a machine would operate at a 10 GHz clock rate and comprise a million gates. Main memory would be semiconductor. Most importantly, the processor itself would dissipate only one watt of power (not including main memory). It is believed that further R&Dcould enhance the clock speed by another factor of 5 to a 50 GHz rate and reduce the power dissipation by another order-of-magnitude. Such advances might yield a one TeraFLOPS processor dissipating approximately four Watts. This is clearly a candidate for the processing component of a thousand-processor PetaFLOPS computing system.