The barriers to significant performance gains beyond a TeraFLOPS include many that are readily apparent. Silicon-based microprocessor clock cycle times range from 40 nanoseconds to 5 nanoseconds. The fastest clocks using gallium arsenide are between 2 and 3 nanoseconds. Increasing clock rates so that cycle times will be below 1 nanosecond is unlikely in the near future because the rate of progress in this area is relatively slow.
Cost is a dominant obstacle. Brute force methods today would result in a PetaFLOPS system estimated to cost hundreds of billions of dollars with reliability problematic and usability anyone's guess. Cost is dominated by memory requirements that, if consistent with previous scaling factors, would require a petabyte of main memory. In today's technology, this would require 100 million components for the memory alone. More generally, cost is influenced heavily by market forces that determine the types and cost of mass produced devices, both largely beyond the influence of the high-performance computing community.
The diameter of the system measured in clock cycles may be extremely long by the standards of contemporary parallel computers. Millions of transactions between processors and memory will be active simultaneously, requiring levels of memory bandwidth, latency hiding, and fine-grain parallelism well beyond (by orders-of-magnitude) the current base of experience. Reliability and programming methodologies must be major considerations because either could result in a system that is unuseable for practical purposes.
Finally, when planning future directions in computer system design, projections for enabling technologies are a crucial source of constraints and guidance. Anticipating trends in underlying technologies is made more difficult by the extended time frame under consideration and the prospect of requiring technologies in the future, now only at their early stage of development.