The existence of a national roadmap for the development of semiconductor technology greatly simplifies the task of visualizing the future capabilities of CMOS devices. The Semiconductor Industries Association sponsored the development and publication of a national consensus roadmap to aid in research and development planning. The essence of the 1992 version of the roadmap is captured in Table 5.1. Unfortunately, the map does not project far enough in time to address the PetaFLOPS challenge.
The roadmap presents a vision of successively reduced feature size CMOS generations extending forward at a three-year intervals. Each new generation can support memory devices of four times greater density that the previous generation. The 1992 map stopped at 0.1 micrometers because reduced insulator thickness was expected to result in undesired conduction mechanisms such as tunneling, and also that subthreshold leakage would restrict device options. It seemed that a paradigm shift to quantum mechanical devices was likely: that the historic CMOS progression would finally end.
Since the 1992 roadmap was prepared, however, additional learning has taken place. Expectations now are that more or less conventional CMOS technology generations will continue until at least the 0.05 micrometer level, and perhaps as small as the 0.025 micrometer level. Also, power dissipation is expected to receive a great deal of development attention, and that the dissipation of even very high-performance chips will be modest. Because the roadmap is a living document, the Semiconductor Research Corporation is hosting planning sessions to revisit the predictions with a view to maintaining a technology plan that is updated every few years, and always extends forward about 15 years. A revised roadmap is expected to be issued in November, 1994.