Memory

Demonstrations of memory chip performance in purely superconductive devices have not been as impressive in density per chip; nevertheless, they have repeated the speed and power features of the logic circuits. The level of research and development effort has been much smaller than that applied to logic circuits. Thus, although only a 4K RAM at 500 picosecond access time has been demonstrated successfully in Japan, layouts have been made for RAM chips expected to have 500 picosecond access time, and recently, sections were built and are under testing. Given the present all-superconductive circuits and what is currently known, it is generally believed that the best path to follow to achieve large memory chips at low power is to implement hybrids: superconductor-semiconductor circuits. It is also expected that proper use of cryogenic CMOS will assist in solving the speed/size requirements. Nevertheless, it is feasible to build purely superconductive ROM and RAM at levels of integration appropriate to ``buffering'' the processor requests.