R&Dto Overcome Barriers and Obstacles

The working group conceived a long-term R&Dapproach with broad program goals over the next ten years. The approach is described below in terms of a five-year program and broad 10-year goals:

• Five-Year Program

Logic

The present fabrication capability to achieve good yield on a 20,000- to 40,000-gate chip should be improved and stabilized. The circuit family would be adopted from the Japanese.

Memory

We must re-evaluate and develop sub-nanosecond memory chips. The state of the art is not as advanced as logic, principally due to a much lower level of effort. The goal is to less than 10 milliwatts per chip with a sub-nanosecond access time. Most important is the development of a cryo-CMOS memory chip. Preliminary work is taking place at a very low level to demonstrate superconducting-semiconducting on-chip hybrids. Sense amplifiers, narrow line interconnects, and enhanced speed due to the cold environment are being evaluated. In addition, one must test the performance improvement of standard CMOS and specially processed CMOS at cryogenic temperatures.

Interconnects

Chip pad configurations up to 350 I/Os at 2.5 gigabytes/sec are presently being developed (e.g., Crossbarat MCC). For impedance and crosstalk reasons, the pad configuration described by MCC for Crossbar and by MITI's Electro Technical Laboratory, namely coaxial I/Os, should be exploited. This would improve greatly the multi-gigahertz frequency behavior of the transition between the chips and their supporting MCM.

It will be critical to establish the MCM technology for a large chip count processor. Thus, a careful test and evaluation of KYOCERA's MCM (built for the MITI/ETL supercomputer four-chip system) is needed at a 10 GHz clock rate. This also requires cooling the MCM properly.

The connections to room temperature will necessarily be at gigahertz rates and most likely will involve transfer rates of terabits/sec. Impedance-matched cables of short () length of this class of performance developed for Crossbar must be improved for both thermal and bandwidth reasons. However, a very attractive technique is to use optical I/O, either by fiber optic cable or free-space interconnect. This would provide outstanding data rates and do so with negligible heat transfer.

To interconnect between processors and from processors to memory, a switching fabric must be available. The present crossbar development needs to be extended in speed or size (or both), and other switches should be evaluated and developed for this purpose.

• 10-Year Goals

Logic

Underlying this goal is the ability to reduce the power by 10 while increasing circuit speed by five. Single flux quantum logic offers both of these features. The logic gates and circuit structures need more detailed demonstrations both in simulation and in fabrication. Also needed is an evaluation of the limits of ``conventional'' voltage state logic; early (i.e., 1970s) circuit structures were shown to have those speed-power properties but were not explored.

The capability to fabricate with good yield will need to be improved by inserting good but standard silicon processing tools. Along with that, design and testing will be further advanced.

Memory

Continual improvement of both cryo-CMOS and superconductive memories will occur, and must occur, by silicon's normal progress and by the practice of superconductive fabrication.

Interconnects

The critical steps required will be the timing and substrate issues introduced by using a clock whose period corresponds to a time-of-flight of roughly for free-space light.

The second major challenge will be the switching interconnect. The architecture and the requisite speed to provide processor-processor and processor-memory connections will require careful, intense work. The third technical improvement will require the use of optic I/Os to achieve the necessary data bandwidths. At this point, one will most likely need to exploit the already demonstrated picosecond soliton propagation of fiber optics and the also demonstrated picosecond response time of superconductive electronics. The interface of this to the room temperature world will be a challenge. As before, the separate parts, the building blocks, must be assembled into a system demonstration to understand and to prove that the technology ``works.''

To achieve the 10-year goals for logic, memory, and interconnects, milestones for the five- and 10-year milestones against which progress can be measured are necessary. These milestones are shown in Table 5.10.

In the first five years, the development program would focus on logic, memory, packaging, interconnection to room temperature, and switching networks. In the second five years (years 6-10), the program would focus on low-power logic, improved memory, optical I/O, and improved switch networks. The key technologies for the entire 10-year program would be cryo-CMOS, CMOS, and superconductive technologies. Important directions for funded research are listed below:

• Cryogenic sub-nanosecond memory
• Optical I/O to cryo
• Low-power circuits
• Very high-density packaging
• Design techniques and tools
• Gigahertz test techniques
• High-reliability cooling.